Various signal processing applications require linear or nonlinear operations on large amounts of data at high data rates. Such operations involve very intensive and repetitive calculations, and thus utilize significant memory allocation and processor time. Conventional computer architectures, which perform computations on data and instructions delivered to and from memory through a single link, are unable to process these large amounts of data efficiently, and thus the overall cost and complexity of the signal processing application can be prohibitive.
This problem has been ameliorated through the development of parallel-pipeline processing architectures, or "systolic processors." A systolic processor generally includes an array of structurally and functionally identical processing elements or "cells." Portions of data fetched from memory are processed by the processing elements in parallel fashion. Systolic processors offer high computational throughput for a given memory bandwidth. Moreover, the modularity of the processing cells facilitates economic implementation of otherwise costly signal processing applications. A conventional systolic processor of the prior art is described in the publication entitled The ESL Systolic processor for Signal and Image Processing, by Yen et al., pp. 265-272, 1981 IEEE Computer Society Workshop on CAPAIDM.
Notwithstanding the advantages of prior art systolic processors, these devices are limited in their functional capability by certain physical constraints. In particular, the various processing elements of the array are typically hard wired together, depending on the desired signal processing application. The requirement that the processing elements be hard-wired limits the types of operations performable by the array to linear transformations, such as vector inner products, matrix multiplication and convolutions. Complex nonlinear operations, however, are not readily implemented by the array. Such operations require transfer of data to a central processor for nonlinear calculations, thus increasing the cost and complexity of the signal processing application.
There is therefore a need for an improved systolic processing architecture which obviates transfer of data to an external processor for nonlinear calculations and which provides economical implementation of both linear and nonlinear signal processing operations.